VHDL Questions and Answers Part-4

1. Which of the following is not defined by the entity?
a) Direction of any signal
b) Names of signal
c) Different ports
d) Behavior of the signals

Answer: d
Explanation: Entity specifies the name of the entity, the ports of the entity and all the information related to that entity. All designs are created using one or more entities. Declaration of ports in an entity includes the name of signals and there directions.

2. Which of the following can be the name of an entity?
a) Nand_gate
c) Nand gate
d) AND

Answer: a
Explanation: The name of entity can be basically any name, except VHDL reserved words. NAND is reserved for nand operation and same applies for AND. The name of entity can’t contain any space character. Therefore, only option A is the only legal word.

3. Which of the following mode of the signal is bidirectional?
a) IN
b) OUT

Answer: c
Explanation: INOUT is the only bidirectional mode for any signal. IN, OUT and BUFFER are unidirectional mode since they specifies the type to be either input or output. INOUT can be used as both an input to an entity and as an output of the entity. We can read as well as assign the value for INOUT type signal.

4. In an assignment statement, OUT signal can be used only to the ___________
a) Left of <= operator
b) Right of <= operator
c) Any side of <= operator
d) Right of := operator

Answer: a
Explanation: OUT signal is used to take an output from any entity. Therefore, we can assign it any value but can’t read any value from this type of signal. So, in an assignment statement, OUT type signal can be used on the left side of <= operator.

5. On which side of assignment operator, we can use the IN type signal?
a) Right
b) Left
c) Both
d) Can’t be used

Answer: a
Explanation: IN signal is for input only. We can read the value from IN signal. Therefore, it can be placed only on the right side of assignment.

6. GENERICs are not declared in the entity.
a) True
b) False

Answer: b
Explanation: The declaration of GENERICs is also done in the entity itself. It is used to declare the constants that can be used to control the structure of behavior of the entity. The Generics are declared before port declarations.

7. What is the difference between OUT and BUFFER?
a) BUFFER can’t be used inside the entity for reading the value and OUT can be
b) BUFFER can only be read whereas OUT can only be assigned a value
c) BUFFER can be read as well as assigned a value but OUT can only be assigned
d) Both are same

Answer: c
Explanation: BUFFER is a unidirectional mode used as an output from the entity. But, the value of BUFFER can be used inside the entity i.e. it can appear on both sides of assignment operator whereas the value of OUT can’t be used inside the entity and can appear on the left side of assignment operator.

8. How to control the structure and timing of the entity can be changed?
a) By using TIME variable in the entity
b) By changing the entity declaration from time to time
c) By using some special code
d) By using GENERICS

Answer: d
Explanation: The structure and timing constraints can be changed by declaring some constant using GENERICS declaration. For example, in the full adder example, number of bits to be added can be declared as array with its size N. This N can be declared as a constant in the GENERIC declaration part of entity. By changing N only, one can change number of bits for the addition.

9. Which of the following can have more than one driver?
a) IN
b) OUT

Answer: d
Explanation: INOUT is the only bidirectional signal. This mode can have more than one driver. Therefore, INOUT can be driven by more than one drivers. All other modes like IN, OUT, BUFFER can have only one driver.

10. Which of the following is the default mode for a port variable?
a) IN
b) OUT

Answer: a
Explanation: IN is the default mode for a port variable. If the mode of any signal is not specified in the port declaration, then it is considered as IN type signal. All other types are needed to be specified at the time of declaration.